a ssm2160/ssm2161 6 and 4 channel, clickless serial input balance/master volume controls information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features digitally-controlled clickless level adjustment ssm2160: six channels ssm2161: four channels master control has 128 1 db steps each channel has 32 1 db steps step sizes can be changed using external resistors high gain accuracy 100 db gain range power on mute excellent audio characteristics: C100 dbu snr (0 dbu = 0.775 v rms, v s = 6 5 v) +10 dbu headroom (v s = 6 5 v) 0.008% thd+n (@ 1 khz, v in = C10 dbu, unity gain) C80 db crosstalk (@ 1 khz) single or dual supply operation applications dolby* pro-logic master volume/balance control home thx? systems dsp soundfield processors automotive audio systems hdtv audio systems rev. a general description the ssm2160 and ssm2161 allow digital control of volume for six and four channels, respectively, with a master level control. clicking normally encountered with resistor-ladder attenua- tors is eliminated by using high performance voltage controlled amplifiers (vcas) in the signal path. the vca control ports are driven by dacs with controlled output rate-of-change to in- sure noiseless volume changes. each channel is controlled by a dedicated 5-bit dac, providing 32 steps of adjustment. in addi- tion, a master 7-bit dac feeds every control port, with 128 steps. therefore, a balance can be achieved among all channels over a 32 step range, and the master control allows adjustment over its entire range while maintaining the desired channel-to- channel balance. master and channel step sizes are nominally 1 db; master step sizes can be reduced by an external resistor. approximately 80 db of attenuation and up to 20 db of gain is possible. upon power-up, the output is automatically muted. the ssm2160/ssm2161 can operate from single supplies of 8 v to 14 v and dual supplies from 4 v to 7 v. an on-chip buffered supply splitter provides an analog common for single- supply applications. *dolby is a registered trademark of dolby laboratories licensing * corporation. ?home thx is a registered trademark of lucasfilm, ltd. functional block diagram shift register and address decoder power supply and reference 7-bit master dac 5-bit channel dac vca to additional channels ssm-2160: six channel ssm-2161: four channel v in v out audio clk data ld write v+ v acom ? obsolete
ssm2160/ssm2161Cspecifications electrical specifications parameter conditions min typ max units audio performance noise v in = gnd, 20 khz bandwidth C100 dbu headroom clip point = 1% thd+n +10 dbu total harmonic distortion plus noise 2nd and 3rd harmonics only a v = 0 db 0.008 tbd % a v = C10 db 0.02 tbd % channel separation any channel to another 80 db analog input input offset voltage 10 mv input impedance 10 k w gain control elements default step size C master a v master = 0 db to C60 db 1.0 db default step size C channel a v channel = 0 db to +20 db 1.0 db gain error relative to same channel a v master = 0 db 0.25 db a v master = C20 db 0.25 db a v master = C40 db 1 db a v master = C60 db 2 db gain match error channel-to-channel; same level setting a v master = 0 db 0.25 db a v master = C20 db 0.25 db a v master = C20 db, a v ch = +20 db 0.25 db a v master = C40 db 1 db a v master = C60 db 2 db power on mute attenuation v in = +10 dbu C100 db analog output output impedance 5 w mute output impedance 5 w output current 2ma minimum resistive load drive 1 k w maximum capacitive drive tbd pf offset voltage channel muted 10 mv control section logic input lo 0.8 v logic input hi 2.0 v logic input current logic lo or hi 1 m a clock frequency 1 2000 khz timing characteristics see timing diagram analog common output output voltage see note 1 C5 +5 % output impedance 5.0 w power supplies supply voltage range dual supply 4 15 v single supply +8 +15 v supply current positive 17 28 ma negative 17 28 ma power supply rejection ratio dual supply tbd db notes 1 analog common output is used in single supply applications. it is nominally half the voltage between v+ and vC, e.g., v + ( v ) 2 . specifications subject to change without notice. (v s = 6 5 v, a v = 0 db, 0 dbu = 0.775 v rms, v in = 0 dbu, f audio = 1 khz, f clk = 250 khz, r l = 10 k v , C40 8 c < t a < +85 8 c, unless otherwise noted. typical specifications apply at t a = +25 8 c.) rev. a C 2 C obsolete
ssm2160/ssm2161 rev. a C3C absolute maximum ratings 1 supply voltage dual supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v single supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+18 v analog input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s analog output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . v s logic input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s operating temperature range . . . . . . . . . . . . . C40 c to +85 c storage temperature . . . . . . . . . . . . . . . . . . . C65 c to +150 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . +150 c lead temperature (soldering, 60 sec) . . . . . . . . . . . . . +300 c thermal characteristics thermal resistance 2 24-pin plastic dip (ssm2160) q ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 c/w q jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 c/w 24-pin soic (ssm2160) q ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 c/w q jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 c/w 20-pin plastic dip (ssm2161) q ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 c/w q jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 c/w 20-pin soic (ssm2161) q ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 c/w q jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 c/w esd ratings 883 (human body) model . . . . . . . . . . . . . . . . . . . . . tbd kv eiaj model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .tbd v notes 1 stresses above those listed under "absolute maximum ratings" may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 q ja is specified for worst-case conditions, i.e., q ja is specified for device in socket for p-dip and device soldered in circuit board for soic package. pin configurations 24-lead epoxy dip and soic 13 16 15 14 24 23 22 21 20 19 18 17 top view (not to scale) 12 11 10 9 8 1 2 3 4 7 6 5 ssm2160 v+ vout2 mstr set mstr out ch set agnd acom vout1 vin4 vout4 vin2 vin1 vout3 vin3 vout5 vin5 write data vin6 vout6 ld v clk dgnd 20-lead epoxy dip and soic 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) ssm2161 v+ vout2 mstr set mstr out ch set agnd acom vout1 vin4 vout4 vin2 vin1 vout3 vin3 write ld v dgnd clk data warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ssm2160/ssm2161 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of func tionality. ordering guide model temperature range package option ssm2160p C40 c to +85 c 24-lead plastic dip ssm2160s C40 c to +85 c 24-lead sol ssm2160s-reel C40 c to +85 c 24-lead sol ssm2161p C40 c to +85 c 20-lead plastic dip ssm2161s C40 c to +85 c 20-lead sol ssm2161s-reel C40 c to +85 c 20-lead sol obsolete
ssm2160/ssm2161 rev. a C4C 1 0.010 0.0005 010 0.1 1
ssm2160/ssm2161 rev. a C5C figure 4. timing diagrams notes 1. an idle hi (clk-h) or idle lo (clk-lo) clock may be used. data is latched on the negative edge. 2. for spi or microwire three-wire bus operation, tie ld to write and use write pulse to drive both pins. (this generates an automatic internal ld signal.) 3. if an idle hi clock is used, t cw and t wl are measured from the final negative transition to the idle state. 4. the first data byte selects an address (msb hi), and subsequent msb lo states set gain levels. refer to the address/data decoding truth table. 5. data must be sent msb first. 6. the ssm2160/ssm2161 will power up with all channel outputs muted, thus preventing "start-up blasting." to insure a smooth start-up, data should be sent to first initialize the master dac, then to set the individual channel dac levels. table i. timing description timing typical symbol description time (ns) t cl input clock pulse width tbd t ds data setup time tbd t dh data hold time tbd t cw negative clk-lo edge to end of write tbd t lw end of load pulse to next write tbd t wd start of write to data tbd t wl end of write to start of load tbd t l load pulse width tbd d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 1 1 1 1 clk data write ld t wl t l t lw t cw t wd t dh t ds t cl 0 0 1 1 0 1 1 0 clk data write ld obsolete
ssm2160/ssm2161 rev. a C6C figure 5. ssm2160 functional diagram (ssm2161 same but with channels 5 and 6 omitted) vca 1 channel dac 1 channel dac 2 channel dac 3 channel dac 4 channel dac 5 channel dac 6 master dac vca 2 vca 3 vca 4 vca 5 vca 6 voltage reference generator shift register and address decoder mstr set mstr out vin1 vout1 vin2 vout2 vin3 vout3 vin4 vout4 vin5 vout5 vin6 vout6 ch set dgnd clk data ld write v+ v agnd acom v+ obsolete
ssm2160/ssm2161 rev. a C7C a. dual supply b. single supply c. single supply using external reference + + 1 2 v+ 0.1? 10? v 0.1? 10? 12 13 dgnd v acom (nc) agnd v+ + 1 2 v+ 0.1? 10? vref out 12 13 dgnd v acom agnd v+ + 0.1? 10? 3 + 1 2 v+ 0.1? 10? 12 13 dgnd v acom (nc) agnd v+ external reference figure 6. ssm2160 power supply connections 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 ssm2160 + 0.1? 10? + 0.1? 10? + 10? r m * out in ch 2 out in ch 4 out in ch 6 data clk out in ch 1 out in ch 3 out in ch 5 v write ld to change step sizes: master dac: *use formula r m = 1400x/(1-x): where x equal desired step size in db. note: step sizes indicated are approximate. figure 7. typical application circuit (dual supply) obsolete
|
